The present invention relates to an apparatus for recovering clock, and in particular to an apparatus for recovering clock and data received either asynchronously or synchronously.
Conventionally, phase lock loops (PLLs) are utilized for recovering clock for data to be received in digital format. A disadvantage of PLLs is that a relatively high number of preamble data bits is required for the PLL to acquire a proper clock signal, and constant reinforcement for this clock signal must be contained within the data to prevent the PLL from unlocking from a dominant frequency detected from the preamble. PLLs typically require about 10 or more bits of preamble for adequately locking onto a dominant frequency. Examples of PLLs are found in U.S. Pat. Nos. 4,385,396; 4,677,648; and 3,980,820, the disclosures of which are incorporated herein by reference.
The inclusion of an excessively long preamble and transition line encoding to maintain a PLL clock can significantly increase a bit rate for a system. In the case of an asynchronous packetized system for transmitting telephone signals along a bus or ring, the overhead can easily exceed 100%. Specifically, for a packet of data containing eight bits with eight preamble bits and 4B5B transition line encoding, the actual data content of any packet is less than half the signal bits actually transported.
According to the related Apple application entitled "Clock Recovery Apparatus" cited above, clock is recovered using edge sampling and comparing techniques. The present invention is an improvement over the invention described therein and includes the further feature of adjusting a frequency of either a subscriber interface unit (SIU) clock or an office interface unit (OIU) clock periodically to insure that clock drift does not allow the frequency of packetized data to differ significantly from the frequency which a receiver believes the incoming data possesses so as to prevent reading errors from occurring, especially within extremely long packets.